Effective graph generation from VHDL descriptions

Abstract

The transformation between a problem description and a data dependency graph is a step that results in a significant reduction of freedom during high-level synthesis. This paper presents an evaluation of different graph generation methods and makes a suggestion on the methods to be employed in the solution of such a problem. High-level synthesis takes its input written in an artificial language, i.e. VHDL or one of several similar languages [1]. These descriptions take the form of functions which must be transformed to a hardware realization using the steps of initial allocation, scheduling and allocation.