Effective extraction of accurate reduced order models for HF-ICs using multi-CPU architectures

Abstract

In this article a fast, accurate and robust parallel algorithm for the extraction of reduced-order models for passive parts of high-frequency integrated circuits is proposed. The core of the reduction procedure is based on vector fitting rational approximation of the circuit functions, which are obtained by finite integration technique. In order to reduce the global computational effort, an original adaptive frequency sampling is used to generate an optimal list of frequency samples. The computationally intensive part of the algorithm is efficiently mapped on a hierarchical multiprocessor architecture. The goal is to reduce the extraction time and to control the accuracy of the extracted reduced-order model.