Effective bitstream compression approaches for high speed digital systems

Abstract

This paper describes the compression techniques to attain high bandwidth and memory requirements which is necessary in high speed embedded systems. The most commonly used bitstream compression technique is Dictionary based code compression (DCC) due to its high compression. In this technique, the bitstream which is not stored in the dictionaries generates it as an uncompressed format that needs large storage space. To mitigate this issue, two effective compression techniques named as Separated split LUT (SSL) and Bitmasked Separated split LUT (BSSL) are proposed to improve the compression ratio (CR) and bit saving rate (BSR).The proposed compression algorithms are coded in VHDL, synthesized using Xilinx ISE 14.2 and implemented in Kintex 7 Field Programmable Gate Array (FPGA).The proposed compression techniques are evaluated for various benchmark processors such as Sha, CRC, Dijkstra, FFT and Susan processor. Sha processor has the lowest bitstream entries and the CR is 59.75% and the CR for CRC, Dijkstra, FFT and Susan processor are 58, 45, 70 and 75, respectively.