Abstract
In this paper, the chemical vapor deposition (CVD) processing for 4H-SiC epilayer is investigated with particular emphasis on the defects and the noise properties. It is experimentally found that the process parameters of C/Si ratio strongly affect the surface roughness of epilayers and the density of triangular defects (TDs), while no direct correlation between the C/Si ratio and the deep level defect Z1/2 could be confirmed. By adjusting the C/Si ratio, a decrease of several orders of magnitudes in the noise level for the 4H-SiC Schottky barrier diodes (SBDs) could be achieved attributing to the improved epilayer quality with low TD density and low surface roughness. The work should provide a helpful clue for further improving the device performance of both the 4H-SiC SBDs and the Schottky barrier ultraviolet photodetectors fabricated on commercial 4H-SiC wafers.
Highlights
As an excellent wide bandgap semiconductor material, 4H-SiC has attracted continuous attention in the last several decades
The results show that the density of triangular defects (TDs) is reduced from 1.3 cm−2 to 0.13 cm−2 with the C/Si ratio decreasing from 1.1 to 0.9
It is found that the reverse current and noise characteristics of 4H-SiC Schottky barrier diodes (SBDs) are highly dependent on the C/Si ratio
Summary
As an excellent wide bandgap semiconductor material, 4H-SiC has attracted continuous attention in the last several decades. We reported the density of other morphological defects in a 4-inch 4H-SiC epitaxial wafer, as well as their probability of causing Schottky diode power device failure [19]. The probability of causing device failure is 100% for TDs and downfalls, while the probability of degrading the reverse breakdown voltage of the device is 2% and 30% for particles and carrots, respectively Among all these morphological defects, the TDs should attract enough attention as the critical device killer. The concentration of the Z1/2 is (0.1–4) × 1013 cm−3 for the commercially available 4H-SiC material, which seriously affects the performance of bipolar devices and photodetectors due to the existence of deep level traps [20]. A large number of studies have shown that the formation of these defects is closely associated with growth temperature, C/Si ratio, thermal oxidation, carbon ion implantation, thermal annealing, in-situ pre-growth etch and cutting angle of SiC substrate, etc. [25,26,27,28,29,30]
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