Effect of the depletion region in topological insulator heterostructures for ambipolar field-effect transistors

Abstract

Formation of a depletion region at the vertically stacked topological insulator $p\text{\ensuremath{-}}n$ heterostructures is one of the effective approaches to minimize residual carrier density in the bulk regions. Here, we report on characterization of field-effect transistor (FET) based on ${(\mathrm{B}{\mathrm{i}}_{0.26}\mathrm{S}{\mathrm{b}}_{0.74})}_{2}\mathrm{S}{\mathrm{e}}_{3}/\mathrm{B}{\mathrm{i}}_{2}\mathrm{S}{\mathrm{e}}_{3}$ topological insulator heterostructures with a vertical $p\text{\ensuremath{-}}n$ junction configuration. The thicknesses of the top $p\text{\ensuremath{-}}{(\mathrm{B}{\mathrm{i}}_{0.26}\mathrm{S}{\mathrm{b}}_{0.74})}_{2}\mathrm{S}{\mathrm{e}}_{3}$ layer vary from $d=8$ to 25 nm with 3-nm constant thickness of the bottom $n\text{\ensuremath{-}}\mathrm{B}{\mathrm{i}}_{2}\mathrm{S}{\mathrm{e}}_{3}$. Even at zero gate voltage, increasing thickness of the top layer inverts the dominant conducting carrier from $n$-type to $p$-type. With applying gate voltage, the effect of depletion region at the interface is clearly revealed as a voltage shift of charge neutral point in ambipolar FET operation. The systematic shift of charge neutral point in FET operation clearly indicates that the formation of depletion region can be explained with conventional semiconductor $p\text{\ensuremath{-}}n$ junction model. In the topological insulator $p\text{\ensuremath{-}}n$ heterostructures, the thickness tuning of both $p$-type and $n$-type layers is quite important to minimize the residual charge density in the whole device region. The band engineering with $p\text{\ensuremath{-}}n$ junction will be further applicable to extract the electrical properties of surface state.