Abstract
In this work, SiC nanowire (NW) FETs are prepared and their electrical measurements are presented. From the samples fabricated on the same substrate, various I-Vs shapes are obtained (linear, non linear symmetric, and asymmetric). With the assistance of simulation, we show that this is a result of different values of Schottky Barrier Heights (SBH) at Source (S) / Drain (D) contacts of FETs. An origin for this might be a non uniformity in annealing, NW doping level and high interface traps density (that pins the Fermi level) as well as the high sensitivity of the metal-NW contacts to local surface contaminations.
Highlights
The majority of the research groups working on NW FETs use metals as S / D areas and they are trying to lower the rectifying SB [1] or even transform them to completely ohmic [2] by proper annealing step
From the samples synthesized on the same substrate using the same metal contacts and device process steps, various I-Vs characteristics shapes are obtained
With the assistance of simulation, we show that this is a result of different values of SB heights at S/D contacts
Summary
The majority of the research groups working on NW FETs use metals as S / D areas and they are trying to lower the rectifying SB [1] or even transform them to completely ohmic [2] by proper annealing step. In the first work on SiC NW FETs [2], the researchers used low work-function metal (Ti) in contact with highly n-type doped nanowire and so the initial SB was suppressed after the annealing leading to ohmic contacts (linear I-V for low Vd ).
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
