Abstract
Tunnel FETs has emerged as a promising candidate to replace the conventional CMOS technology in the near future owing to its sub-60 mV/dec subthreshold slope. In this paper we have explored the effects of asymmetric channel doping in Tunnel FET devices through extensive modeling and simulation approaches. A Halo doped pocket implantation at the source end is expected to decrease the width of the depletion region resulting in considerable increase in the device current. A compact surface potential model is developed based on the 2-D Poisson's equation followed by the calculation of band energy. The effect of doping of the pocket implantation is studied that helps to optimize the level of HALO doping and thereby, the length of the doped region. The obtained results are compared with a device simulator Sentaurus TCAD and a good agreement is observed.
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