Effect of silicon substrate microroughness on gate oxide quality

Abstract

The process induced surface microroughness of both the silicon substrate and top surface of 15 nm gate oxide were investigated by atomic force microscopy. Varying degrees of surface microroughness on the Si and on the gate oxide were induced by timed wet silicon etch (750:1 HNO3:HF solution). The Rms roughness of the initial silicon substrate was <0.2 nm, while the value increased to 0.65 nm after extended etch. For short etch times, the initial Si surface roughness was reproduced at the gate oxide surface. The average electrical field strength required to maintain a fixed current density of 1.5×10−5 A/cm2 was found to increase with decrease of the gate oxide surface roughness.