Effect of serialized routing resources on the implementation area of datapath circuits on FPGAS

Abstract

In this work, we investigate the effect of serialization on the implementation area of datapath circuits on FPGAs. With ever-increasing logic capacity, FPGAs are being increasingly used to implement large datapath circuits. Since datapath circuits are designed to process multiple-bit wide data, FPGA routing resources, which typically consist of a significant amount of FPGA area, are routinely being used to transport multiple-bit wide signals. Consequently, it is important to design efficient routing architectures for transporting multiple-bit wide signals on FPGAs. Serialization, where several bits of a signal are first time-multiplexed and then transported over a single wire, has been effectively used to increase the I/O bandwidth of FPGAs. Recent work has proposed to use serialization to increase the area efficiency of FPGA routing resources for transporting multiple-bit wide signals. Most of the work, however, has focused on circuit-level design issues. Little work has been done on the overall effect of serialization on the area efficiency of FPGAs. In this work, we investigate the overall effect of serialization on the area efficiency of FPGAs. We propose a detailed FPGA routing architecture, which contains a set of serialization routing resources, and its associated routing tool. Using the architecture and the tool, we measure the effect of serialization on active area and track count. We found that, for benchmarks that contain four-bit wide datapath circuits, serialization can achieve a maximum active area reduction of 6.4% and a routing track reduction of 29%.