Abstract
Thermal stress induced by annealing the Cu filling of through-silicon vias (TSVs) requires further investigation as it can inhibit the performance of semiconductor devices. This study reports the filling behavior of TSVs prepared using direct current and pulse current Cu electrodeposition with and without pre-annealing. The thermal extrusion of Cu inside the TSVs was studied by observing the extrusion behavior after annealing and the changes in grain orientation using scanning electron microscopy and electron backscatter diffraction. The bottom-up filling ratio achieved by the direct current approach decreased because the current was used both to fill the TSV and to grow bump defects on the top surface of the wafer. In contrast, pulse current electrodeposition yielded an improved TSV bottom-up filling ratio and no bump defects, which is attributable to strong suppression and thin diffusion layer. Moreover, Cu deposited with a pulse current exhibited lesser thermal extrusion, which was attributed to the formation of nanotwins and a change in the grain orientation from random to (101). Based on the results, thermal extrusion of the total area of the TSVs could be obtained by pulse current electrodeposition with pre-annealing.
Highlights
The through-silicon via (TSV) is an important technology for connecting dies in 3D interconnects to overcome the physical and economic limitations associated with wiring and enhance the performance of semiconductor devices (Beica et al, 2008; Motoyoshi, 2009; Cao et al, 2013; Pan et al, 2018)
The TSV filling ratio using a direct current decreased with increasing average current density because of the current lost to the additional growth of bump defects on the surface (Supplementary Figure 1)
The filling ratio for pulse current electrodeposition was higher than that of direct current deposition because the top surface of the wafer was strongly suppressed and the current was only used for TSV filling instead of defect formation
Summary
The through-silicon via (TSV) is an important technology for connecting dies in 3D interconnects to overcome the physical and economic limitations associated with wiring and enhance the performance of semiconductor devices (Beica et al, 2008; Motoyoshi, 2009; Cao et al, 2013; Pan et al, 2018). Cu with its high electrical conductivity is used to fill TSVs by deposition methods, such as chemical vapor deposition, physical vapor deposition, and electrodeposition. After TSV filling, Cu is typically subjected to high-temperature processes such as annealing to stabilize its microstructure (Yang et al, 2011). Annealing induces thermal stress, which can cause reliability problems such as degraded device performance in keep-out zone and thermal extrusion of Cu (De Wolf et al, 2011; Heryanto et al, 2012; Ryu et al, 2012; Guo et al, 2013). A keep-out zone, or keep-away zone, is an area where the transistor is affected by thermal stress from the mismatched coefficients of thermal
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