Effect of plasma and staging time on the underfill voids in fine pitch flip-chip package

Abstract

Underfill voids have been one of the major reliability concerns in flip-chip packaging specially in a fine pitch. Therefore, monitoring of process based root causes of the void formation is significantly important. In this study, 7.5×7.5 Si die was bonded on two 17 mm *17 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> substrates viz. S1 and S2 to prepare a-ISO µm pitch flip chip package. Effect of two process parameters such as plasma and staging time was observed on void formations. Plasma cleaning of both substrate was done for 1 minute. Before underfill dispensing, staging of units was performed for 4, 6 and 8 hours, and void formation was observed using confocal scanning acoustic microscopy (C-SAM). Differences in void formations among S1 and S2 are related to the change in surface of solder mask. Therefore, optical pro filer was used to detect the changes in surface roughness of solder mask with plasma and staging time. Whereas, formation of different chemical bonds before and after plasma was analyzed using x-ray photoelectron spectroscopy (XPS). Also, water contact angle on S1 and S2 was evaluated before and after plasma cleaning. As a result of this study, percentage unit failure was increased with increasing staging time. This is attributed to changes in surface roughness, and amount of O-C=O, C-O, C-C bonds on solder mask. Contact angle on secondary non-bump area may or may not be representative of underfill wettability due to surface roughness difference with bump area on one substrate supplier but similar surface roughness between bump and non-bump area on another substrate supplier.