Effect of pad design (SMD/NSMD), via-in-pad, and reflow profile parameters on voiding during the lead-free solder bumping process

Abstract

There is a continuous need for higher density memory modules for applications like servers, telecommunications, and networking. Memory modules with package stacked Dynamic Random-Access Memory (DRAM) devices were developed for these applications. Stacked DRAM packages were developed by stacking monolithic DRAMs using interposer Printed Circuit Boards (PCBs). A standard Surface Mount Technology (SMT) process was used for stacking DRAMs. Solder bumping is a cost effective alternative to solder balling in the DRAM stacking process. The solder bumping process encompasses solder paste screen printing onto the PCB, followed by reflow soldering. In spite of cost savings associated with the solder bumping process, it can result in relatively more voiding than solder balling process. Hence, it is important to study the effect of various factors on solder voiding during the solder bumping process. The PCB real estate and design constraints necessitate the need for via-in-pad technology and the use of Solder Mask Defined (SMD) pads. In this paper, the effect of Non-Solder Mask Defined (NSMD) pads, SMD pads, via-in-pad (with/without), and reflow profile parameters on solder voiding were studied. Key words: Solder bumping, void, lead-free solder, reflow process, stacking, SMD, NSMD, via-in-pad.