Effect of Negative Capacitance MOSFET Devices on Circuit Applications

Abstract

The conventional complementary metal-oxide-semiconductor (CMOS) technology is coming to an end due to its large power dissipation and self-heating. This can be solved by utilizing the ‘negative capacitance’ (NC) effect. To observe this negative capacitance, a ferroelectric (FE) material is needed to be used instead of an insulator in transistors. In this work initially, a normal Verilog A modeling of the transistor has been used to study its characteristics and then gradually employed a ferroelectric layer in the gate stack by modifying and inserting Landau Khaltnikov (L-K) model parameters in the model. This modification allows us to observe a reduction in voltage across the ferroelectrics, i.e., a negative capacitance and subthreshold swing less than 60 mv/decade. The analysis of NC transistor is performed to find the role of ferroelectric layer thickness and three ferroelectric coefficients α, β and γ. By using these concise models, the performance of various digital circuits has been evaluated with NC transistors.