Abstract
In Thin Small Non-Leaded Packages (TSNP) design, heat resistance tape (i.e. RT321 and RT321+CD1) were used as leadframe carrier throughout TSNP assembly manufacturing line. These carrier acts as package backbone during molding process and were removed during detape process as to expose Cu pad (2nd interconnection) before plating process. However, under un-optimized parameter condition in TSNP assembly manufacturing line, the heat resistance tape shows inconsistence performances and contribute high assembly yield losses. The current paper investigates the effect of heat resistance tape on torn tape and excess solder defect in detape and plating process respectively. Torn tape defect occurred during mechanical peeling (remove heat resistance tape as to expose Cu pad). Whereas, excess solder defect were detected after Sn plating process, excess solder defined as x and y pad dimension out of specification based on Infineon Technologies Process Control. The DOE's input factor of Detape (i.e. Temperature and Peeling Method), and Sn Plating (i.e. Current, Loading Method and Conveyor Speed) were established with the help of CEDA software. RT321+CD1 tape resulted to be best fit in TSNP manufacturing line compared to RT321 tape due to tape physical properties compatibility. However, at high detape temperature, low plating current and high conveyor speed, performances of RT321 tape are comparable with RT321+CD1.
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