Abstract
The internal electrical characteristics of an 800-V 9-A 0.7-Ω silicon power MOSFET are investigated using a distributed modelling approach. A cad tool has been developed to automatically extract layout parasitics and create an equivalent spice-like netlist of the device under investigation. The distributed model is employed to investigate the performance of the device during a turn-off switching at different values of the gate fall time. Simulations show that reducing the gate fall time contributes to increase the internal current imbalance leading to current density overshoots, referred to as hot spots. Moreover, faster switching operation forces current density to crowd towards the slowest parts of the device which in turn degrades the overall device ruggedness. These results demonstrate that the proposed modelling approach allows accurate simulation of the internal current distribution identifying the regions where hot spots are more likely to occur.
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