Effect of lateral straggle parameter on Hetero Junction Dual Gate Vertical TFET

Abstract

In this Article, the effects of lateral straggle parameter variation and Temperature variation have been investigated on Hetero Junction Dual Gate Vertical TFET. Although the TFET is a viable alternative to the MOSFET, the performance of the device is dependent on the accuracy of the fabrication process. The ion implantation technology is applied for the regions of Source/Drain during the fabrication process to realise the variation in tilt angle. As a result of this process, Dopants from the source and drain areas are extended into the channel, which has a substantial impact on the device's performance. The impact of lateral straggle is implemented by considering it in the TCAD simulation. The performance of the Hetero Junction Dual Gate Vertical TFET is examined by the 0–6 nm variation in the lateral straggle parameter. When the lateral straggling parameter (σ) is set at higher values, the greater electron tunnelling rate results in an increase in the on current. Various parameters such as intrinsic capacitances like gate to source capacitance (Cgs), gate to drain capacitance (Cgd), and total capacitance (Cgg), gate charge, electric field, surface potential, transconductance are studied in Hetero Junction Dual Gate Vertical TFET for various σ values.