Effect of interfacial InZnO conducting layer on electrical performance and bias stress stability of InAlZnO thin-film transistors

Abstract

InAlZnO (IAZO) thin-film transistors (TFTs) containing an InZnO (IZO) conducting layer at the interface between the IAZO channel layer and the gate insulator layer were fabricated. The electrical characteristics and bias stress stability of the IAZO/IZO TFTs were examined as functions of the thickness of the interfacial IZO conducting layer (which was set as 1, 2, and 3 nm), and optimal performance of the TFTs was achieved when the thickness was 2 nm. The optimized IAZO/IZO TFT showed a saturation mobility of 52.6 cm2/V·s, which is superior to that of a pristine IAZO TFT (29.8 cm2/V·s). Furthermore, the threshold voltage shifts under positive and negative bias stress conditions simultaneously improved from +2.1 V to +1.0 V and from −1.1 V to −1.0 V, respectively. IAZO/IZO interfaces were analyzed by X-ray photoelectron spectroscopy to elucidate the cause of the improved device characteristics.