Effect of interconnection delay on liquid nitrogen temperature CMOS circuit performance

Abstract

In this work, the effect of interconnection delay on the performance of CMOS circuits operated at liquid nitrogen temperature is examined. The interconnect is modeled as a distributed RLC line driven by an optimal configuration of cascaded inverters. Using measured aluminum thin film resistivities, the delay time is predicted as a function of interconnect length at both 300 K and 77 K for typical 0.8 7micro;m CMOS technologies. It is shown that the driver resistance, rather than the interconnect resistance itself, limits performance and the improvement in delay time achieved through low temperature operation is close to a factor of two irrespective of interconnect length.