Effect of High-K Dielectrics in Different Doping Concentrations in a Junctionless GAA Nanowire Transistor Structure

Abstract

In this research, the impact of gate dielectric, doping concentration and channel length on the transfer characteristics of cylindrical gate-all-around junctionless transistor is resolved by using the CVT model approach by using TCAD Silvaco Atlas. Short channel effect parameters like Drain induced barrier lowering (DIBL), Threshold Voltage Roll-off (TVRO), Subthreshold Swing (SS), on current and off current ratio (I on /I off ) for the CG structure of n-channel gate-all-around JLNW transistor are analyzed. Depletion of carriers in the device layer of cylindrical gate-all-around JLNWT are more effective in comparison with tri-gate, double gate, rectangular gate-all-around JLNWT. In quintessence, the Cylindrical gate-all-around JLNW transistor exhibits better transfer characteristics with a high I on /I off ratio, SS is near about to the 60mV/decade which is ideal and highly reduced DIBL. Moreover, the Cylindrical gate-all-around JLNW transistor has better control over the carriers which flow through the device layer. In short, a Cylindrical gate-all-around JLNW transistor established as a promising candidate having benefits of reduced short channel effects and low power operation at nanoscale technology.