Abstract
In this paper, with the help of calibrated 2-D simulations, we report a detailed study on the effect of drain induced barrier enhancement on the subthreshold swing and OFF-state current of a short channel MOSFET. We demonstrate that the presence of gate-on-drain overlap in a short channel MOSFET leads to drain induced barrier enhancement (DIBE). We show that as a result of DIBE, a MOSFET can achieve near ideal subthreshold swing, diminished DIBL, constant threshold voltage and improved $\text{I}_{\mathrm {ON}}/\text{I}_{\mathrm {OFF}}$ ratio at room temperature, without being affected by channel length variations.
Highlights
When compared to a MOSFET, the TFET exhibits a sub-60 mV/decade subthreshold swing (SS) and lower leakage current
We study the effect of drain induced barrier enhancement (DIBE) on the DC performance of a short channel MOSFET focusing on the average subthreshold swing, ION/IOFF ratio and threshold voltage
Thickness, tSi = 10 nm, equivalent oxide thickness (EOT) under the gate and gate-on-drain overlap, tox = 1 nm, gate work function ΦG = 4.5 eV, gate-on-drain overlap work function ΦOL is varied from 4.5 eV to 5.5 eV, source and drain doping concentrations ND = 1×1019 cm-3 and channel doping concentration NA = 1×1017 cm-3
Summary
When compared to a MOSFET, the TFET exhibits a sub-60 mV/decade subthreshold swing (SS) and lower leakage current. To the best of our knowledge, using gate-on-drain overlap, there is no reported work on (i) enhancing the barrier height at the drain-channel junction of a MOSFET and (ii) analyzing its impact on Drain Induced Barrier Lowering (DIBL), SS and ION/IOFF ratio in short channel MOSFETs for channel lengths less than 50 nm. Those papers that have studied the impact of gate-on-drain overlap are related to tunnel field effect transistors. Our results indicate that the presence of DIBE causes the average subthreshold swing to be near ideal and makes the threshold voltage and ION/IOFF ratio at room temperature independent of channel length variations
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