Abstract
STI (Shallow-Trench-Isolation) and ILD (Inter-layer-Dielectric polishing steps are important polish stages in FEOL (Front-End- of-Line) due to the early stage of transistor device formation. In recent years, ceria based slurries have been used in STI and ILD applications, and the slurry has demonstrated self-stopping capability for better planarization efficiency and wider process window. Many studies have been done on the mechanism of why ceria has better selectivity than silica, particularly at the interface between wafer and abrasive interaction. This paper will focus on the effect of pad properties as well as slurry additives through a detailed pad characterization and slurry formulation study of ceria-based slurry. Polishing tests have been performed to investigate the interaction between wafer, slurry and pad through in-situ friction coefficient measurements. Consumables selection recommendation and polishing mechanism will be discussed as well in this paper.
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