Effect of checker board failure on yield improvement in 0.15 /spl mu/m embedded flash memory

Abstract

This work is aimed at the yield improvement with root cause definition on checker board (CB) failure inside flash matrix cell by key process optimizations as well as a novel process introduction in 0.15 /spl mu/m embedded flash memory device. It is reported that the root cause of very gross CB failure was mainly due to the abnormal leakage from flash access transistor (FAT) inside flash matrix cell array and high voltage (HV) devices in the charge pump & decoder system. Furthermore, it turned out that threshold voltage (Vt window) for programming and erasing is one of big modulators to cause CB failures. To tackle these problems, a new approach to reduce HV device leakage by introducing Ti-rich TiN film as CoSi/sub 2/ capping layer is proposed and confirmed by direct experiment. Concurrently, the optimizations of both FAT punch-through implantation and post-cleaning process just after the formation of ONO film as inter-poly dielectric in stacked-gate (FG/CG) were carried out so as to minimize FAT off current and to improve Vt window, respectively, leading to the successful elimination of CB failures.