Effect of boron penetration on the stress induced leakage current in PMOS structures with p+ doped polysilicon gate

Abstract

Boron penetration from a p+ polysilicon gate through a gate oxide and into the silicon substrate is a critical issue for the formation of the gate stack in the submicron complementary metal oxide semiconductor devices. Boron incorporation results in positive flat-band voltage ( V fb) shifts and p-type metal oxide semiconductor threshold voltage instabilities. In this work, we propose a method which allows comparison of degradation in oxide layers with different boron contents, and so with different flat-band voltages. It has been demonstrated that boron incorporation increases the stress induced leakage current at an injected charge but also at breakdown. The charge to breakdown is also affected by the boron diffusion in the oxide. The same trend is observed by increasing the stress current density. All these results may be explained by an increase of the trap creation efficiency under stress. Nevertheless, if the stress induced leakage current appears to be a measure of a defect density in the oxide, the stress induced leakage current at breakdown does not correspond to a critical defect density needed for breakdown.