Abstract
In microelectronic packaging technology for three-dimensional integrated circuits (3D ICs), Cu-to-Cu direct bonding appears to be the solution to solve the problems of Joule heating and electromigration (EM) in solder microbumps under 10 in diameter. However, EM will occur in Cu–Cu bumps when the current density is over . The surface, grain boundary, and the interface between the Cu and TiW adhesion layer are the three major diffusion paths in EM tests, and which one may lead to early failure is of interest. This study showed that bonding strength affects the outcome. First, if the bonding strength is not strong enough to sustain the thermal mismatch of materials during EM tests, the bonding interface will fracture and lead to an open circuit of early failure. Second, if the bonding strength can sustain the bonding structure, voids will form at the passivation contact area between the Cu–Cu bump and redistribution layer (RDL) due to current crowding. When the void grows along the passivation interface and separates the Cu–Cu bump and RDL, an open circuit can occur, especially when the current density and temperature are severe. Third, under excellent bonding, when the voids at the contact area between the Cu–Cu bump and RDL do not merge together, the EM lifetime can be more than 5000 h.
Highlights
Due to the ending of Moore’s law on the miniaturization of two-dimensional integrated circuits (2D IC), 3D ICs through chip stacking technology is the most promising way to continuously improve the chip performance [1,2,3]
In 3D ICs, because there are many reliability issues in shrinking solder joints [4,5,6,7,8,9,10], Cu-to-Cu direct bonding technology has been introduced to scale down the diameter of joints [11,12,13,14]
If the bonding strength can sustain the tensile stress from the thermal mismatch of materials, EM–induced Cu diffusion and vacancy diffusion can last for a long time, until the growth of voids along the passivation interface leads to failure
Summary
Due to the ending of Moore’s law on the miniaturization of two-dimensional integrated circuits (2D IC), 3D ICs through chip stacking technology is the most promising way to continuously improve the chip performance [1,2,3]. Cu (nt-Cu) [32,33] was adopted to fabricate nt-Cu microbumps because nt-Cu columnar was performed through lithography to define the pattern of Cu–Cu bum grains have a (111) surface for low-thermal-budget bonding [15] and good mechanical protect the. Mension mentioned above might vary slightly because of the sample fabrication proThe current of the EMTest test was 1.5 A, and the chip was put on a hotplate EM damages were expected to occur faster near the PSV opening and RDLs. As Joule heating occurred significantly during EM tests [38], the actual temperature was measured through the method of the temperature coefficient of resistance (TCR). Three chips of each bonding condition were fabricated without UF dispensing to perform the pull test, so the average bonding strength of each Cu–Cu bump could be measured. A table listing the pull test of bonding strength is shown later
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