Abstract
In this work a 6 Transistor SRAM circuit is designed and simulated with FDSOI device whose Channel length (LCH) and Buried Oxide (BOX) thickness (Tbox) is varied to observe the effects on the circuit performance in terms of stability, power consumption and delay. The LCH and Tbox are considered separately, the simulation is performed on same circuit considering four values of Tbox for each LCH to comprehend the effects of these parameters. The Static Noise Margin (SNM) is discussed with great importance as it gives a clear idea about the stability of the stored data which is satisfactory for FDSOI device based SRAM performance. The delay and standby power consumption also suggest that this device is suitable for constructing memory circuits.
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