Effect of annealing time on Si/SiO 2 interface property for CMOS fabricated on hybrid orientation substrate with ATR method

Abstract

In this work, we report an investigation into the interface property of CMOS devices using hybrid orientation technology (HOT). For nMOSFETs, devices with increased defect-removal annealing time brought about a significant reduction in the charge pumping current and low-frequency noise. This result implies that the amorphization/templated recrystallization (ATR) process-induced defects at the recrystallized (1 0 0) regions are further repaired, and consequently achieved the “low-trap-density” of the Si/SiO 2 interface. On the other hand, for pMOSFETs, no obvious distinction can be observed between devices on both HOT wafers, indicating that the treatment of defect-removal anneal would not affect bonding (1 1 0) regions. In addition, on HOT wafers, the low-frequency noise of pMOSFETs is attributed to a fluctuation in the mobility of free carriers, while the unified model, i.e., the carrier-number fluctuation correlated mobility fluctuation, dominates the low-frequency noise of nMOSFETs.