Edge termination strategies for a 4 kV 4H–SiC thyristor

Abstract

Thyristors able to block 4kV have been fabricated and characterised. The experimental forward current is 1.3A @ VAK=10V for a 9mA gate current during 550ns. The device active area is 2.3mm2. The devices and their edge terminations have been designed using numerical simulations. Two different edge terminations have been envisaged (mesa and a combination of mesa and JTE). A SiO2 passivation layer also improves the forward blocking voltage depending on the sign and the magnitude of the effective charge density in the oxide. The mesa protection is not enough to allowing the thyristor to block 5kV, due to the low etching rate in SiC. Thus, a mesa/JTE protection has been used. The influence of the etching depth, the JTE dose and length on the forward blocking voltage of the thyristor has been studied in details. Simulation results have allowed designing the devices, not far from the optimal structure. The best results of the forward blocking voltage are 4kV for the mesa protected thyristor, while the mesa/JTE combination yields 3.6kV. Furthermore, experimental results confirm the simulations concerning the influence of the oxide thickness on the forward blocking voltage. The better results for the mesa protected thyristor are due to a lower interface SiC/SiO2 charge density provided by the different oxidation processes (at different foundries).In addition, the comparison between experiments and simulations allows estimate the effective charge density of the SiO2 layer in 1012–5×1012cm−2 range for the two fabricated thyristors. The improvement in the forward blocking voltage must pass through an improvement of the passivation layer. Passivation still remains a technological key step to obtain SiC high-voltage devices.