Edge effect aware crosstalk avoidance technique for 3D integration

Abstract

3D integration is one of the most promising solutions for the scaling of future integrated circuits (ICs). Nevertheless, the 2D metal wires and 3D through silicon vias (TSVs) are frequently performance bottlenecks of 3D ICs, due to their high capacitive crosstalk, which can be reduced by a coding approach. In this work we show that existing TSV crosstalk avoidance codes (CACs) are impractical for real applications due to the edge effects in TSV arrays. Additionally, these 3D CACs do not reduce the metal wire crosstalk. This work presents a crosstalk avoidance approach for 3D ICs which overcomes both limitations. The method remaps the bits of existing 2D CACs onto a TSV array in a way that results in the minimum possible TSV crosstalk. Experimental results, obtained by circuit simulations in combination with an electromagnetic field solver, show that the presented technique can reduce the crosstalk of TSVs and metal wires by about 30 % and 50 %, respectively. In comparison, with higher hardware costs, existing 3D CACs only reduce the TSV crosstalk by a maximum of 11.45 %, while providing no optimization of the metal wire crosstalk.