EDA performance and clock synchronization over a wireless network: Analysis, experimentation and application to semiconductor manufacturing

Abstract

Shrinking process tolerances due to decreasing device sizes and increasing chip complexity in semiconductor manufacturing are motivating efforts to improve methods of equipment data acquisition (EDA). Prior work shows that the lack of precise time-stamping and clock synchronization is a critical hindrance to reliable data acquisition and real-time process control systems. The ultimate goal in the development of EDA standards for performance is to meet industry demands such as modularity, reconfigurability, decentralization, interoperability and low cost. While precision in timing addresses some of these requirements, the need for scalable modularity, flexibility and lower cost is also responsible for a recent interest in performing EDA functions over wireless networks. This paper presents an analysis of data acquisition and clock synchronization performance over a wireless network. Clock synchronization accuracy in a real world EDA environment was determined by using a configurable fab-wide EDA system simulator designed to recreate the specific equipment configurations, network traffic patterns, and data acquisition protocols used by industry standard equipment. The data packets from the EDA simulator were routed through a wireless network testbed described in Section III. The results show that while wireless networks are significantly noisier in terms of time delay variation, a sufficient level of time-synchronization among wireless nodes should be achievable, given additional improvements for meeting semiconductor manufacturing requirements. Hence, time stamping of EDA data can greatly improve data quality, and open up avenues for the design of controllers that are better suited to leverage wireless networks.