Economical Failure Analysis for Microprocessors

Abstract

A technique is presented for isolating the failing node within a microprocessor type chip. The computer-driven production-tester is used to identify the failing instructions prior to failure analysis. In the laboratory, simple two or three instruction test-patterns are programmed into a n × 16 (1 ? n ? 255) memory buffer and then clocked into the device under test in an endless repetitive loop. Internal microprobing is then used to check the internal control lines and registers to localize the failure. The technique has been used to isolate failure mechanisms on wafers and in packaged devices from a variety of sources, including environmental stress failures and field returns. The article demonstrates the feasibility of performing efficient, accurate, and low cost failure analysis on microprocessors. The essential features are an efficient laboratory administrative system, concise and accurate input documentation, knowledge of the internal workings of each chip, the memory buffer-testing technique, and an accurate microprobing capability. Results at Mostek indicate that a single, well trained technician with occasional engineering supervision can successfully analyze an average of two moderately difficult failing devices per day. Since a usual sample of devices will contain some simple failures, an average daily throughput of about four to five devices has been realized. The capital outlay (less than $1000) for the equipment (exclusive of pre-existing lab equipment such as an oscilloscope) has been confined to the construction and components cost of the memory buffer and its associated interconnect wiring.