Economic Evaluation of Design-for-Test Alternatives for Microelectronics Products

Abstract

Cost-of-Ownership (COO) models, developed for integrated circuit (IC) fabrication equipment, can be extended to the various cost domains of microelectronics design and development cycles. Details of a COO model developed to evaluate design for test (DFT) alternatives are given, together with the results of application to case studies of different test scenarios. Scan and Built-in-Self-Test (BIST) are popular DFT solutions. Mixed scan/BIST alternatives are shown to reduce overall costs through improved fault coverage, which justifies extra design overhead and slight performance degradation in most cases. For all but relatively simple IC products economic benefits from DFT solutions are demonstrated.