Echelon: a multilayer detailed area router

Abstract

We present a general multilayer area router for performing detailed routing in integrated circuits. This router is based on a novel grid construction scheme which considers the differing design rules of the routing layers and produces more wiring tracks than a uniform grid scheme. Our router is very general and flexible and is designed to handle all the physical constraints of a CMOS custom cell layout problem for an arbitrary number of routing layers. The router has been incorporated into the Custom Cell Synthesizer project at MCC. It has produced better results than uniform gridded routers and improved the capability of the system by providing routing flexibility and supporting features needed to handle a wide range of design styles in generating CMOS custom cells.