Echelle grating for silicon photonics applications: integration of electron beam lithography in the process flow and first results

Abstract

We present the technology steps to integrate an Echelle grating in the process flow of silicon-organic hybrid (SOH) modulators or related active devices. The CMOS-compatible process flow on SOI substrates uses a mix of optical i-line lithography and electron beam lithography (EBL). High speed optical data communication depends on wavelength divisions multiplexing and de-multiplexing devices like Echelle gratings. The minimum feature sizes vary from device to device and reach down to 60 nm inside a modulator, while the total area of a single Echelle grating is up to several mm2 of unprocessed silicon. Resist patterning using a variable shape beam electron beam pattern generator allows high resolution. An oxide hard mask is deposited, patterns are structured threefold by EBL and are later transferred to the silicon. We demonstrate a 9-channel multiplexer featuring a 2 dB on-chip loss and an adjacent channel crosstalk better than -22 dB. Additionally a 45-channel Echelle multiplexer is presented with 5 dB on chip loss and a channel crosstalk better than -12 dB. The devices cover an on-chip area of only 0.08 mm2 and 0.5 mm2 with a wavelength spacing of 10.5 nm and 2.0 nm, respectively.