Early power-grid seed creation to reduce power-Signoff effort

Abstract

Power-grid design is one of the key steps in achieving target performance of a modern System-on-Chip (SoC). With shrinking nodes the noise margin is reducing and hence it's imperative to have a robust power-grid. Power delivered to each design component in the layout directly impact the component delay, hence efficient power delivery is also an important requirement for the SoC. Current implementation tool's delay models don't take into account the effect of voltage-drop on the delays; hence, impact of voltage drop on performance is known only at the silicon. On the flip-side, over designing of the power grid will lead to routing congestion as well and may lead the increase in the chip area. Currently all the methods for the “early” power-grid is at the floorplan level, this is still late since, the chip size and area is committed to the customer, making a change here would be expensive and hence undesired. Methodology presented in this paper, with basic technology and design information will provide an optimal seed power-grid for a new design that would be correct by construct to achieve the desired performance goals, at the specification stage. Designer can add power-grid cost as part of the new chip analysis and predict the optimal area to meet the chip power requirements before floorplan stage. Experimental data shows a 35% average improvement in the routing utilization between the power-grid design based on the proposed methodology as compared to the traditional approach.