Early evaluation for phased logic circuits using BDDS and MVL

Abstract

Phased logic (PL) is a design style for binary-valued asynchronous logic circuits. A performance enhancement known as early evaluation (EE) allows for increased throughput in PL circuits. PL circuits are produced using clocked circuit descriptions as input and then automatically mapping them into PL equivalents while adding optimization features. In the process of adding the EE performance enhancement, a special known as a function is extracted from the partitions. Here, we describe a method for finding candidate trigger functions using BDDs and a technique for combining multiple trigger functions to support a single circuit partition using multiple-valued logic (MVL). Experimental results show that these methods yield better coverage as compared to using a single trigger function.