Dynamic-Gate-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

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In this paper, degradation behaviors of bridged-grain (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are systematically characterized and investigated. Device degradation exhibits a two-stage behavior, which is related to pulse falling time ( $t_{f}$ ). A faster $t_{f}$ brings a larger ON-current ( $I_{\mathrm{\scriptscriptstyle ON}}$ ) increase in the first stage and a larger $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage. Electron trapping/injection into gate oxide and dynamic hot carrier effect are found to be responsible to $I_{\mathrm{\scriptscriptstyle ON}}$ increase in the first stage and $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage, respectively. Compared with normal poly-Si TFTs, BG poly-Si TFTs show much more reliable performance under the same dynamic gate stress. The larger $I_{\mathrm{\scriptscriptstyle ON}}$ increase in the first stage in BG poly-Si TFTs is attributed to the enhanced vertical electric field in the channel near the gate oxide, while the much smaller $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage is attributed to lateral electric field reduction caused by the sharing of the field across multiple reversely biased junctions inside the active channel. Incorporated with transient simulations, the degradation mechanisms for both the first stage and the second stage are elucidated. In addition, the impact of the first-stage degradation on the second-stage degradation is also clarified.