Abstract
Modern embedded systems are being modeled as Reconfigurable High Speed Computing System (RHSCS) where Reconfigurable Hardware, that is, Field Programmable Gate Array (FPGA), and softcore processors configured on FPGA act as computing elements. As system complexity increases, efficient task distribution methodologies are essential to obtain high performance. A dynamic task distribution methodology based on Minimum Laxity First (MLF) policy (DTD-MLF) distributes the tasks of an application dynamically onto RHSCS and utilizes available RHSCS resources effectively. The DTD-MLF methodology takes the advantage of runtime design parameters of an application represented as DAG and considers the attributes of tasks in DAG and computing resources to distribute the tasks of an application onto RHSCS. In this paper, we have described the DTD-MLF model and verified its effectiveness by distributing some of real life benchmark applications onto RHSCS configured on Virtex-5 FPGA device. Some benchmark applications are represented as DAG and are distributed to the resources of RHSCS based on DTD-MLF model. The performance of the MLF based dynamic task distribution methodology is compared with static task distribution methodology. The comparison shows that the dynamic task distribution model with MLF criteria outperforms the static task distribution techniques in terms of schedule length and effective utilization of available RHSCS resources.
Highlights
Microprocessors are at the core of high performance computing systems and they provide flexibility for wide range of applications at the expense of performance [1]
The microprocessor acts as softcore processor that executes software tasks described in High Level Language (HLL) whereas the Reconfigurable computing (RC) architecture Field Programmable Gate Array (FPGA) acts as hardcore processor that reconfigures its hardware for the behaviour of hardware tasks described in Hardware Description Language (HDL)
Reconfigurable High Speed Computing System (RHSCS) platform is realized on Virtex-5 FPGA (Virtex5 XC5VLX110T), as shown in Figure 5, using Xilinx EDK where a MicroBlaze softcore processing element (PE) is configured in part of the reconfigurable area of FPGA and the rest of reconfigurable area is used for configuration of multiple Reconfigurable Logic Units (RLUs), memory, and communication protocols
Summary
Microprocessors are at the core of high performance computing systems and they provide flexibility for wide range of applications at the expense of performance [1]. There are hybrid systems such as reconfigurable system on chip (RSoC) [4] and MOLEN architecture [3] in the literature that have integrated both microprocessor and FPGA to support software as well as hardware tasks in an application. A hybrid computing platform called Reconfigurable High Speed Computing System [3, 4] (RHSCS) having integrated softcore PE (MicroBlaze) and hardcore PE (RLUs) configured on a single chip FPGA minimizes communication cost and supports both software tasks and hardware tasks execution. The RHSCS can provide optimal intermediate computing platform for execution of software tasks and hardware tasks exist in distributed applications.
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