Dynamic Robust Single-Event Upset Simulator

Abstract

This paper presents the dynamic robust single-event upset simulator, which is a novel framework for fault injection on hardware (via onchip debugging) and simulation testbeds (via the Simics® full-system simulator from Wind River Systems). Typically, radiation-hardened processers are used for space computing; however, commercial off-the-shelf processors can provide higher performance and lower costs. Although commercial devices are susceptible to radiation-induced faults, fault-injection testing can be used to qualify these devices for use in space. The de facto standard for fault injection is radiation-beam testing, which is often prohibitively expensive and time consuming. The current methodology provides a means to iteratively decrease design vulnerabilities through rapid fault injection before beam testing. Additionally, the methodology can supplement beam-test results by targeting injections at individual components of interest that are difficult to isolate in beam tests. The current fault-injection mechanisms leverage on-chip debuggers and simulation checkpoints, allowing the framework to target a wide range of system components for injection. The injection capabilities and analysis features of the framework are demonstrated by presenting fault-injection results for an image-processing application on two different processor architectures (PowerPC and ARM®) in both hardware and simulation.