Dynamic power reduction through clock gating technique for low power memory applications

Abstract

Clock gating is an effective technique for minimizing dynamic power in sequential circuits. This paper aims at reducing the power of a dual port register memory by removing the unwanted switching activity on a major portion of the clock network using clock gating. To realize this, two register based Random Access Memories (RAMs) have been designed, one with clock gating and the other without clock gating. Their performance on various Xilinx Field Programmable Gate Array (FPGA) platforms has been discussed to emphasize the effect of this technique at various technology nodes. A reduction of 25% to 70% in the dynamic power and 15% to 32% in the total power of the memory has been observed. This reduction in the power of the memory is attributed to the register level application of clock gating technique The designs have been synthesized, implemented and simulated using Xilinx ISE design suite 13.4 and the power has been estimated using XPower Analyzer.