Dynamic planning of local congestion from varying-size vias for global routing layer assignment

Abstract

This work is the first to present global routing models for capturing the impact of local congestion caused by varying-size vias. The models are then incorporated to dynamically drive a proposed layer assignment algorithm. A typical characteristic of advanced technology nodes is significantly-high variation in wire sizes that may exist between adjacent metal layers. Routing from a global cell (g-cell) to its top metal layer results in using a via which may be up to twice the size of unit wire track within that g-cell. This results in significant decrease in the available routing tracks that could pass the boundaries of the g-cell. Ignoring this issue hampers the effectiveness of traditional global routing algorithms due to acting as, now, a significant source of mismatch with the detailed routing stage. Based on these observations, we propose “via-aware edge overflow” and “edge-aware via overflow” models for capturing the impact of both unstacked and stacked vias of arbitrary sizes during global routing. Our models can be used to drive any layer assignment algorithm and replace the traditional edge overflow and via overflow metrics. To show the impact of our models, we also incorporate them in a proposed two-stage layer assignment algorithm and compare with a competitive layer assignment technique. This is also the first work to actually evaluate the impact of global routing solutions using a commercial detailed router. In our experiments we report less number of DRC violations by only changing the layer assignment at global routing, and detailed route using the Olympus-SoC of Mentor Graphics.