Dynamic partitioning method for piecewise‐linear VLSI circuit simulation

Abstract

AbstractThis paper presents a method for dynamically partitioning circuit equations for time‐point relaxation‐based electrical circuit simulation techniques. the non‐linear element characteristics are approximated by piecewise‐linear (PWL) functions. the dynamic partitioning is carried out at every iteration during the solution process by comparing integers representing region numbers in the PWL functions, and only those PWL elements that change regions are involved in the repartitioning process. In many instances the circuit is automatically partitioned into completely d.c.‐disconnected subcircuits, which result in speeding up the convergence of the relaxation process. the approach has been implemented in a computer program for transient analysis of MOS VLSI circuits. Computational speeds of two orders of magnitude or more as compared to standard circuit simulation have been observed in solving small circuits on a serial computer without much loss in accuracy. the speed improvement is expected to be higher as the size of the circuit increases. Simulation using the dynamic partitioning method on a parallel computer indicates an efficient use of the processors, and corresponding improvement in speed.