Dynamic Partial Reconfiguration in FPGAs for DSP Applications

Abstract

DSP Application needs to speed-up in computation time can be achieved by assigning complex computation intensive tasks to hardware and by exploiting the parallelism in algorithms.These applications need high performance as well as cost efficient design. Reconfigurable systems offer us a potential for computation acceleration due to its software-like programmable nature of the parallel processing units. Run-time configuration explores a novel research area for reconfigurable hardware to further speedup the processing speed by eliminating the configuration overhead with the overlapping of execution time. Dynamic partial reconfigurable FPGAs offer new design space with a variety of benefits: reduce the configuration time and save memory as the partial reconfiguration files (bitstreams) are smaller than full ones. This paper introduces a simple reconfigurable system and focuses on the newest dynamic partial reconfiguration design flow.