Dynamic filter cache for low power instruction memory hierarchy

Abstract

Filter cache (FC) is effective in achieving energy saving at the expense of some performance degradation. The energy savings, here, comes from repeated execution of tiny loops from energy efficient FC. The absence of cacheable loops leads to performance degradation in such FC structures. Therefore, we propose a simple dynamic FC scheme, which detects the opportunity for use of the FC and enables (or disables) it dynamically. Thus providing (slightly reduced) energy savings at minimal performance degradation. A combination of the predictive filter cache with the above schemes reduces the performance and energy penalty. For the benchmarks simulated with 256 byte FC, the average performance degradation is 1.13% with the proposed scheme compared to 2.47% with just the predictive filter cache. With the same configuration, the resulting energy reduction is 42.77%. Finally, the proposed dynamic filter cache scheme is inherently simple and hence it lends well for VLSI efficient implementation.