Dynamic fault injection model for on-chip 2D mesh network

Abstract

In current scenario, On-Chip Network advances to fulfill higher bandwidth demand rises by chip multiprocessor (CMP). Each nanometer technology of transistor is giving high performance but becoming more fault prone. Hardware faults are injected inside the network to determine its behavior by using some offline fault injection mechanism. This model address permanent and transient fault injection mechanism either at run time or compile time. The paper proposes a fault injection model of hardware faults using software based fault injection technique. Fault injection model is implemented by extending Nirgam Simulator. The effectiveness of injection model can be seen by analyzing results of latency and throughput in different scenario.