Dynamic error tracking and supply voltage adjustment for low power

Abstract

Amongst many techniques to reduce power consumption of chips, lowering the supply voltage is known to be the most effective one. However, lowering the supply voltage of chips too much down to near the threshold voltage of transistors causes the logic delay to vary exponentially with intrinsic and extrinsic variations such as process variations, temperature variations, and aging, and thus forces the designer to set increased timing margin or use more advanced techniques such as adaptive voltage scaling, where the supply voltage is adjusted by tracking timing errors due to the variations. This paper proposes a technique for adaptive supply voltage adjustment that minimizes power consumption in the near-threshold voltage region while satisfying a given constraint on error rate. It can be used in signal processing applications where intermittent errors are tolerated. The technique employs a current sensing completion detector for tracking errors and increases/decreases the voltage if the error rate is too high/low. We show that, for the average case, our approach tracks errors better than other approaches. We also show that it achieves 42% and 54% power savings for an error rate of 0.1% and 5%, respectively, for the TT corner at 25°C