Abstract
A new technique to deal with simultaneous testing of delay and stuck-at faults in digital integrated circuits is proposed. It consists of sensitising a path in the digital circuit under test and then incorporating it in a ring oscillator to test for delay and stuck-at faults in the path. This procedure should be exercised for all, or at least critical, paths in the circuit. This test technique can be used along with scan techniques or implemented as a complete built-in self-test solution.
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