Dynamic delay variation behaviour of RNS multiply-add architectures

Abstract

In this paper we investigate the impact of intra- and inter-die variations on the delay sensitivity of certain Residue Number System (RNS) arithmetic circuits in comparison to ordinary binary arithmetic logic. The timing yield of systems that contain multiply-add units (MAC) is of great importance since they dominate important applications such as digital signal processing. Specifically, we employ two different delay models for the estimation of delay distributions of RNS and binary MAC architectures. Our analysis quantitatively proves that RNS MAC architectures that use bases of the form {2n − 1, 2n, 2n + 1} demonstrate better normalized delay variation than binary MAC architectures to characterize both their static timing behaviour and the timing behaviour taking into account the sensitizable paths. Furthermore, it is shown that certain simplified RNS MAC architectures outperform conventional RNS MAC architectures in terms of the μ + α · σ delay variation metric.