Dynamic computational blocks for bit-level systolic arrays

Abstract

Integrated dynamic logic trees with latches provide cost effective circuit techniques for building massively pipelined, systolic, computational blocks operating at the bit level. Recent results have demonstrated that dynamic pipelines are capable of very high switching speeds with appropriate circuit design techniques. In this paper we trade some of this speed for much higher functionality of each logic block. The resulting throughput rate remains sufficiently high for useful applications, but results in substantial area and power savings. Design techniques for the individual logic trees (switching trees) are based on simple graph theoretic rules. Examples are shown to support the technique.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>