Dwell time effect on the barrier layer capacitor structure in CaCu3Ti4O12 ceramic

Abstract

The effects of sintering process on electrical properties of CaCu3Ti4O12 ceramics were investigated. Impedance spectroscopy analysis demonstrates that these materials are electrically heterogeneous. This electrically heterogeneous microstructure plays a major role for the giant dielectric constant in CaCu3Ti4O12 ceramic. We found a very high dielectric constant (~123,000) with low loss (~0.25) at room temperature. Cole–Cole plots provide effective evidence of the high dielectric constant supported by the barrier layer capacitor model. Activation energy was found to be 0.06eV and 0.46eV corresponding to grain and grain boundary, respectively which proves that the grain boundaries are more resistive than grains. Our results indicate that the polarization relaxation has a close relation to the activation energy of CaCu3Ti4O12 ceramics. This study will help to design CaCu3Ti4O12 based materials and lead to more applications in the microelectronics devices.