DVFS method of memory hierarchy based on CPU microarchitectural information

Abstract

Due to limited battery power that devices have, an efficient DVFS (Dynamic Voltage and Frequency Scaling) algorithm is important. DVFS applies not only to the CPU, also the shared cache and memory associated with the CPU. The CPU and these memory hierarchy interact with each other, however, their DVFS methods are operated independently. Although there have been many discussions to reduce the memory access latency of CPU, the conventional DVFS technique does not relieve memory stall (the state during which CPU is stalled waiting for a memory access) effectively due to individual DVFS methods. In this article, we propose a new DVFS method, which alleviates the memory stall and reduces CPU power consumption utilizing microarchitectural information. Our proposed method identifies the layer on the memory hierarchy that mainly generates the memory stall and determines the optimal frequency of CPU and memory hierarchy that achieve a system-wide power optimization, without degrading the performance. In our experiments, our proposed method improved IPC (Instruction Per Cycle) by 11%, reduced MSPC (Memory Stall Per Cycle) by 26% and reduced power consumption by 5% compared to a conventional DVFS method.